HP/PA-RISC support

The HP PA-RISC (Precision Architecture - Reduced Instruction Set Computing) was developed by Hewlett-Packard as a high-performance RISC architecture for its enterprise-class workstations and servers. It was designed to simplify instruction execution and optimize system throughput, providing a balance between computational power and hardware efficiency.

PA-RISC follows a load/store model, separating memory access from arithmetic and logic operations, which helps streamline the processor pipeline and improve execution speed. The architecture uses fixed-length instructions and a large register file to minimize memory access latency and enable efficient instruction scheduling. Unlike some RISC peers, PA-RISC avoids features like branch delay slots, aiming for a more straightforward and consistent execution model.

64-bit HP/PA-RISC 2.0

In 1996 the HP/PA-RISC ISA was extended to 64 bits, with this revision named PA-RISC 2.0. It also added fused multiply–add instructions, to accelerate certain floating-point intensive algorithms, as well as the MAX-2 SIMD extension, which further helps accelerating multimedia applications.

Despite its strong performance in its era, PA-RISC eventually became a legacy architecture as HP transitioned to the Itanium platform in collaboration with Intel. It remains notable for its role in high-end computing during the 1990s and early 2000s.